EDI8G32130C 128kx32 sram module 1 EDI8G32130C rev. 0 1/98 eco #9700 128kx32 static ram cmos, high speed module features 128kx32 bit cmos static random access memory ? access times bicmos: 10 and12ns cmos: 15, 20, 25ns ? individual byte selects ? fully static, no clocks ? ttl compatible i/o high density package ? jedec standard pinouts ? 72 pad simm, no. 405 ? common data inputs and outputs single +5v (10%) supply operation pin configurations and block diagram the EDI8G32130C is a high speed 4 megabit static ram module organized as 128k words by 32 bits. this module is constructed from four 128kx8 static rams in soj pack- ages on an epoxy laminate (fr4) board. four chip enables (e?-e3) are used to independently enable the four bytes. reading or writing can be executed on individual bytes or any combination of multiple bytes through proper use of enables. the EDI8G32130C is offered in a 72 pad simm package, which enables four megabits of memory to be placed in less than 1.3 square inches of board space. all inputs and outputs are ttl compatible and operate from a single 5v supply. fully asynchronous circuitry requires no clocks or refreshing for operation and provides equal access and cycle times for ease of use. four pins, pd1 to pd4, are used to identify module memory density in applications where alternate modules can be interchanged. pd1=open pd2=open pd3 = open pd4 = vss pin names a?-a16 address inputs e?-e3 chip enables w write enable g output enable dq?-dq31 common data input/output vcc power (+5v10%) vss ground nc no connection electronic designs incorporated ? one research drive ? westborough, ma 01581usa ? 508-366-5151 ? fax 508-836-4850 ? electronic designs europe ltd. ? shelley house, the avenue ? lightwater, surrey gu18 5rf united kingdom ? 01276 472637 ? fax: 01276 473748 http://www.electronic-designs.com 32 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 33 34 35 36 nc nc pd3 pd4 vss pd1 pd2 dq0 dq8 dq1 dq9 dq2 dq10 dq3 dq11 vcc a0 a7 a1 a8 a2 a9 dq12 dq4 dq5 dq6 dq7 dq13 dq14 dq15 vss w\ a15 a14 e1\ e0\ 1 2 3 4 5 6 7 8 9 64 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 65 66 67 68 69 70 71 72 e3\ e2\ a16 vss dq16 dq17 dq18 dq19 a10 a11 a12 g\ dq24 dq25 dq26 dq27 a3 a4 a5 vcc a6 dq28 dq29 dq30 dq31 a13 dq20 dq21 dq22 dq23 vss nc nc nc nc nc a?-a16 w g e? e1 e2 e3 dq?-dq7 dq8-dq15 dq16-dq23 dq24-dq31 17 8 8 8 8
2 EDI8G32130C rev. 0 1/98 eco #9700 EDI8G32130C 128kx32 sram module absolute maximum ratings* recommended dc operating conditions dc electrical characteristics parameter sym conditions min max units operating power icc1 w, e = vil, ii/o = 0ma, supply current min cycle 680 ma standby (ttl) power icc2 e 3 vih, vin vil or supply current vin 3 vih 120 ma full standby power icc3 e 3 vcc-0.2v 40 ma supply current cmos vin 3 vcc-0.2v or vin 0.2v input leakage current ili vin = 0v to vcc 20 a output leakage current ilo v i/o = 0v to vcc 20 a output high voltage voh ioh = -4.0ma 2.4 -- v output low voltage vol iol = 8.0ma -- 0.4 v *typical: ta = 25c, vcc = 5.0v (f=1.0mhz, vin=vcc or vss) parameter sym max unit address lines ci 45 pf data lines cd/q 20 pf chip enable line cc 20 pf write line cn 45 pf ac test conditions input pulse levels vss to 3.0v input rise and fall times 5ns input and output timing levels 1.5v output load 1ttl, cl = 30pf voltage on any pin relative to vss -0.5v to 7.0v operating temperature ta (ambient) commercial 0c to +70c storage temperature -55c to +125c power dissipation 4 watts output current 20 ma parameter sym min typ max units supply voltage vcc 4.5 5.0 5.5 v supply voltage vss 0 0 0 v input high voltage vih 2.2 -- 6.0 v input low voltage vil -0.3 -- 0.8 v (note: for tehqz,tghqz and twlqz, cl = 5pf) e w g mode output power h x x standby high z icc2/icc3 l h l read dout icc1 l l x write din icc1 output l h h deselect high z icc1 these parameters are sampled, not 100% tested. *stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. capacitance truth table
EDI8G32130C 128kx32 sram module 3 EDI8G32130C rev. 0 1/98 eco #9700 ac characteristics read cycle note 1: parameter guaranteed, but not tested. *bicmos read cycle 1 - w high, g, e low read cycle 2 - w high symbol 10ns* 12ns* 15ns 20ns 25ns parameter jedec alt. min max min max min max min max min max units read cycle time tavav trc 10 12 15 20 25 ns address access time tavqv taa 10 12 15 20 25 ns chip enable access telqv tacs 10 12 15 20 25 ns chip enable to output in low z (1) telqx tclz 3 3 3 3 3 ns chip disable to output in high z (1) tehqz tchz 5 6 8 10 12 ns output hold from address change tavqx toh 3 3 3 3 3 ns output enable to output valid tglqv toe 5 5 6 13 15 ns output enable to output in low z (1) tglqx tolz 0 0 0 0 0 ns output disable to output in high z(1) tghqz tohz 4 4 5 8 10 ns tavav tavqv tavqx data 2 a q address 1 address 2 data 1 tghqz telqv telqx e g q tehqz a tavav tglqv tglqx tavqv
4 EDI8G32130C rev. 0 1/98 eco #9700 EDI8G32130C 128kx32 sram module note 1: parameter guaranteed, but not tested. *bicmos ac characteristics write cycle write cycle 1 - w controlled symbol 10ns* 12ns* 15ns 20ns 25ns parameter jedec alt. min max min max min max min max min max units write cycle time t avav twc 10 12 15 20 25 ns chip enable to end of write telwh tcw 7 8 10 15 20 ns twleh tcw 7 8 10 15 20 ns address setup time tavwl tas 0 0 0 0 0 ns tavel tas 0 0 0 0 0 ns address valid to end of write tavwh taw 7 8 10 15 20 ns taveh taw 7 8 10 15 20 ns write pulse width twlwh twp 7 8 10 15 20 ns teleh twp 7 8 10 15 20 ns write recovery time twhax twr 0 0 0 0 0 ns tehax twr 0 0 0 0 0 ns data hold time twhdx tdh 3 3 3 3 3 ns tehdx tdh 3 3 3 3 3 ns write to output in high z (1) twlqz twhz 0 5 0 6 0 7 0 10 0 12 ns data to write time tdvwh tdw 5 6 7 12 15 ns tdveh tdw 5 6 7 12 15 ns output active from end of write (1) twhqx twlz 2 2 2 3 3 ns a e w d q tavav telwh tavwh twlwh tavwl tdvwh twhdx twhqx high z twlqz data valid twhax
EDI8G32130C 128kx32 sram module 5 EDI8G32130C rev. 0 1/98 eco #9700 write cycle 2 - e controlled a w e d q tavav tavel tehax tdveh tehdx teleh taveh data valid high z twleh package description ordering information package no. 405 72 pad simm part number speed (ns) package no. bicmos edi8g32130b10mmc 10 405 edi8g32130b12mmc 12 405 part number speed (ns) package no. cmos EDI8G32130C15mmc 15 405 EDI8G32130C20mmc 20 405 EDI8G32130C25mmc 25 405 3.984 .400 .625 max. .250 .050 typ. 3.750 2.045 1.992 .250 .125 dia. (2x) .062 r. (2x) .125 min. .213 max. 4.255 max. p1 electronic designs incorporated ? one research drive ? westborough, ma 01581usa ? 508-366-5151 ? fax 508-836-4850 ? electronic designs europe ltd. ? shelley house, the avenue ? lightwater, surrey gu18 5rf united kingdom ? 01276 472637 ? fax: 01276 473748 http://www.electronic-designs.com electronic designs inc. reserves the right to change specifications without notice. cage no. 66301
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